The PowerPC 440EP embedded processor offers exceptional performance, designflexibility, and robust features geared to demanding Imaging, industrialcontrol, networking and other embedded applications. With speeds of up to533MHz, PowerPC Book E Architecture, and a rich peripheral mix, PowerPC 440EPprocessors are ideally suited for a wide range of high-performanceapplications.Features: * 440 core and DDR interface connect to CoreConnect PLB4 o 100-133MHz, 128-bit data read and write buses, 36-bit address bus o Bridge to PLB3, 100-133MHz, for PCI, EBC, Ethernet, and OPB peripherals * On-chip Double Data Rate (DDR) SDRAM controller o 32-bit interface with optional ECC o 13-bit addressing o 1.1 GBps peak data rate o Support for 4 banks of up to 256MB, maximum capacity of 1GB o Support for 64, 128, 256, and 512Mb DDR devices, with CAS latencies of 2, 2.5, or 3 * PCI interface o 32-bit PCI V2.2, with 3.3V interface, at frequencies of up to 66MHz o Multiple read prefetch and write post buffers o Ability to boot processor from PCI bus memory * USB o USB 1.1 host, MAC and PHY o USB 2.0 Device MAC o USB 2.0 device MAC UTMI or USB 1.1 device PHY device supports 6 end points (3 in, 3 out), 1024 Byte FIFO (double buffering of 512 byte packets) * FPU o 5 stage FPU with 2.0 MFLOPS/MHz (SP/DP) o Hardware support for IEEE 754 o Single-precision and double-precision operation o Single cycle throughput on most instructions o Thirty-two 64-bit floating point registers * External bus controller o 50-66MHz o 8-bit or 16-bit external data bus width o Up to 30-bit address bus o Support for up to 6 ROM, EPROM, SRAM, Flash, or slave peripheral I/O devices o External master support * Nand Flash controller o Block-oriented device, accessed in a manner much like diskette drives with pages, blocks, and, in some devices, zones or districts o 1 to 4 banks of Nand Flash supported on EBC o Direct interfacing to: Discrete Nand Flash devices (up to 4 devices) and SmartMedia Card socket (22-pins) o Device sizes 4MB-256MB supported o 512-byte + 16-byte or 2KB + 64-byte device page sizes supported o Boot-from-Nand: Execute a linear sequence of boot code out of single page of 1st block (512- bytes) o Support DMA to allow direct, no-processor-intervention block copy from Nand Flash out to SDRAM - ECC providing single bit error correction and double bit error detection in each 256-bytes of stored data o Chip selects shared with EBC * DMA controller o 4 independent channels supporting internal and external peripherals