The CHAMP-WB is one of Curtiss-Wright's family of user-programmable Virtex-7 FPGA-based computing products, designed to meet the needs of challenging embedded high-performance digital signal and image processing applications. The CHAMP-WB is targeted specifically at wide-band, low latency applications that require large FPGA processing, wide input/output requirements, with minimal latency. When combined with the 25 GS/s ADC module, featuring 25 GS/s 8-bit ADC technology from Tektronix, an extremely high performance wide-band receiver can be created. The combined card-set is called the CHAMP-WB-A25G and joins the other members of the CHAMP-WB product family.
The CHAMP-WB-A25G couples the dense processing resources of a single large Xilinx Virtex-7 FPGA with a high-bandwidth 25 GS/s 8-bit ADC module in a commercial grade 6U OpenVPX (VITA 65) form factor module. Rugged options will be available in the future. The 25G ADC module can also operate in a dual channel 12.5 GS/s mode. The CHAMP-WB-A25G complements this processing capability with a data plane directly connected to the FPGA with support for Gen2 Serial RapidIO (SRIO) or Aurora up to 10.3 Gbps. Alternate fabrics can also be supported with different FPGA cores. A Gen3 (PCIe) switch connected to the Expansion Plane provides a way for a single host card, such as the VPX6-1957, CHAMP-AV8 or CHAMP-FX4 to control multiple card sets in the CHAMP-WB product family, without utilizing data-plane bandwidth. Two 64-bit 4 GB DDR3L memory banks provide 8 GB of on-card data capture capability. An auxiliary x4 SerDes link and 16 LVDS pairs provide additional I/O capability.